Method and apparatus for detecting a packet error in a wireless communications system with minimum overhead using embedded error detection capability of turbo code

ABSTRACT

The need for separate CRC bits is eliminated by taking advantage of what has been determined to be an embedded error detection capability in a turbo code itself to perform error detection following turbo decoding. Specifically, since the two constituent encoders of a turbo encoder that are used to encode a data packet produce two systematic codes that share the same systematic bits one code, one is used to serve as the parity check for the other. The sign of the log likelihood ratio (LLR) of each systematic bit in a block of decoded data calculated at the end of a turbo decoding cycle is compared with the sign of the LLR of each corresponding bit that was calculated at a previous turbo decoding cycle. If the signs of the LLRs for each comparison do not agree, then a packet error is determined to have occurred; otherwise no packet error is detected.

TECHNICAL FIELD

This invention relates to wireless communications, and moreparticularly, to detecting a turbo-coded packet error at the receiver ina wireless communications system.

BACKGROUND OF THE INVENTION

In wireless communications systems, such as those operating inaccordance with 3GPP2 CDMA2000-1× standards and 3GPP UMTS W-CDMAstandards, a turbo code has been adopted for data transmission on boththe uplink and downlink due to its superior error correctingcapabilities. To detect the residue errors that cannot be corrected bythe turbo decoder, Cyclic Redundancy Check (CRC) code bits are appendedto the packet data before the encoder at the transmitter. A CRC check isthen performed at the receiver on the decoded packet to determinewhether a pass or fail results.

FIG. 1 shows a high-level block diagram of wireless communicationssystem that uses turbo encoding for error correction and CRC for errordetecting. This block diagram is applicable to both 3GPP2 and 3GPPsystems at the conceptual level. At the transmitter 101, which can beeither within a mobile terminal or a base station, a CRC circuit 102determines the CRC bits to be appended to a data packet on input 103that is to be transmitted to receiver 104. Turbo encoder 105 thenencodes the resultant block of data. The turbo-encoded packet is thenprocessed by the physical channel processing circuitry 106, whichperforms such functions, for example, as spreading, scrambling,modulating and multiplexing for transmission over propagation channel107 in accordance with the whatever system standards are being employed.At receiver 104, the physical channel processing circuitry 108 performsthe opposite functions of circuitry 106, including de-multiplexing,demodulation, descrambling and despreading, to produce at its output aset of soft symbol metrics representing the data at the output of turboencoder 105 in the transmitter. Turbo decoder 109 then processes thesesoft symbol metrics to produce a block of bits at its output thatincludes the CRC bits appended to the data packet on input 103 at thetransmitter 101 by CRC circuit 102. Using the same methodology employedby CRC circuit 102 in the transmitter 101, CRC checker 110 performs aCRC check by calculating the CRC from those bits within the decoded datablock at the output of turbo decoder 109 that correspond to thetransmitted data packet. If the CRC determined by CRC checker 110matches the CRC in the block of bits at the output of turbo decoder 109,then the received packet has passed its CRC check and no packet error isdetected. CRC checker 110 then outputs a CRC Pass and the decoded datapacket on outputs 111 and 112, respectively. If the CRC determined byCRC checker 110 doesn't match the CRC in the decoded block of bits atthe output of turbo decoder 109, then the CRC has failed and a packeterror is detected. CRC checker 110 then outputs a CRC Fail on output111, which fail is reported to the higher layer. Disadvantageously, CRCbits introduce overhead, and when the data block size is small, theoverhead can be large. For example, in 3GPP2, the smallest data blocklength for the turbo code is 174 bits. The CRC for this block sizecomprises 12 bits thereby introducing an overhead of 10log₁₀(1+12/174)=0.29 dB. For 3GPP, the smallest data size for the turbocode is 40 bits. When a CRC of 24 bits is used, the overhead is 10log₁₀(1+12/40)=2.04 dB. It is desirable, therefore, to reduce theoverhead introduced by CRC bits while still retaining the errordetecting functionality that a CRC check affords.

SUMMARY OF THE INVENTION

The inventors have realized that advantage can be taken of an embeddederror detection capability in the turbo code itself to perform errordetection following turbo decoding, thereby eliminating the need forseparate CRC bits. Specifically, the inventors have realized that sincethe two constituent encoders of a turbo encoder that are used to encodea data packet produce two systematic codes that share the samesystematic bits, one code can serve as the parity check for the other.In particular, in accordance with an embodiment of the invention, abit-by-bit comparison is made between the detected systematic bitswithin a block of bits at the end of a turbo decoding cycle withcorresponding detected systematic bits at the end of any previous turbodecoding cycle. If all the bits do not match, then a determination ismade that a packet error has occurred; otherwise no packet error isdetected. In particular, the sign of the log likelihood ratio (LLR) ofeach systematic bit in a block of decoded data calculated at the end ofa turbo decoding cycle is compared with the sign of the LLR of eachcorresponding bit that was calculated at any previous turbo decodingcycle. If the signs of the LLRs for each comparison do not agree, then apacket error is determined to have occurred; otherwise no packet erroris detected.

In a first embodiment of the present invention, at the end of aplurality of turbo decoding iteration cycles, where a turbo decodingiteration cycle is defined as a turbo decoding cycle in which a firstturbo constituent code is decoded followed by a turbo decoding cycle inwhich a second turbo constituent code is decoded, the signs of the LLRsdetermined for each systematic bit in one of the two constituent codesare compared with the signs of the LLRs determined for eachcorresponding systematic bit in the other of the two consistent codes.If the signs of the LLRs are not the same for each correspondingsystematic bit, then a packet error is determined to have occurred;otherwise no packet error is detected. In a second embodiment, the signsof the LLRs determined for each systematic bit at the end of a pluralityof turbo decoding iteration cycles are compared with the signs of theLLRs for corresponding systematic bits at the end of the immediateprevious turbo decoding iteration cycle. As in the first embodiment, ifthe signs of the LLRs are not the same for each corresponding systematicbit, then a packet error is determined to have occurred; otherwise nopacket error is detected.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows a block diagram of a prior art wireless communicationssystem employing separate CRC coding and turbo encoding;

FIG. 2 is a block diagram of a prior art turbo encoder;

FIG. 3 is a block diagram of a prior art turbo decoder;

FIG. 4 is a flowchart detailing a first embodiment of the presentinvention for determining whether a packet error has occurred; and

FIG. 5 is a flowchart detailing a second embodiment of the presentinvention for determining whether a packet error has occurred.

DETAILED DESCRIPTION

As afore noted, turbo coding is widely used in third generation wirelesssystem such as 3GPP and 3GPP2, as well as in broadband fixed wirelessIEEE802.16 systems and in satellite communications. Turbo coding is awell known in the art type of coding using a concatenation of twocomponent codes (see, e.g., C. Berrou and A. Glavieux, “Near OptimumError Correcting Coding and Decoding: Turbo-Codes,” IEEE Trans. Commun.,vol 44, pp. 1261-1271, October 1996, and J. Hagenauer, “IterativeDecoding of Binary Block and Convolutional Codes,” IEEE Trans.Information Theory, vol. 42, pp. 429-445, March 1996). At the decoder,soft-decision decoding is performed on both received codes generatingsoft outputs (log-likelihood ratios). Specifically, decoding is splitbetween the two codes by two decoders, one decoder exchanging the softoutput with the other decoder after its own decoding, with the decodingbeing carried out multiple times, in a ping-pong manner, so that eachiteration generates better quality more robust soft outputs. Thisiterative principle is similar to that of the turbo engine from whencethe name “turbo codes” has been derived.

FIG. 2 shows a block diagram of an example of a rate ⅓ turbo encoder asis used in 3GPP wireless communications systems. The structure of thisturbo encoder is a Parallel Concatenated Convolutional Coder (PCCC) withtwo identical eight-state ½ constituent systematic convolutionalencoders 201 and 202 and one turbo code internal interleaver 203.Interleaving (and de-interleaving at the decoder) is performed tominimize the interactive effect that burst errors could impart to thelog likelihood ratios determined for each component code at the decoder.

The transfer function of the eight-state constituent code for the PCCCis given by: $\begin{matrix}{{{G(D)} = \left\lbrack {1,\frac{g_{1}(D)}{g_{0}(D)}} \right\rbrack},} & (1)\end{matrix}$whereg ₀(D)=1+D ² +D ³,andg ₁(D)=1+D+D ³.

When a data packet consisting of a set of K bits {x_(j)} equal to x₁,x₂, . . . , x_(K), is inputted to the encoder, the entire packet isinterleaved by internal interleaver 203 in a manner that is known to thedecoder for de-interleaving purposes. The K bits within the interleavedpacket, {x′_(j)}, are then sequentially inputted to the secondconstituent encoder 202 at the same time the K non-interleaved bits{x_(j)} of the packet are sequentially inputted to the first constituentencoder 201. Constituent encoders 201 and 202, which are essentiallyidentical, each includes three shift registers 204, which are all set atan initial value of zero before any of the packet bits are inputted. Aseach x_(j) bit is inputted, encoder 201 codes that same bit into itselfas a systematic bit, x_(j), while also forming a parity bit, z_(j). Theparity bit is determined by the encoder structure comprising the shiftregisters 204 and modulo-2 adders 205 and is formed from a combinationof previous input bits as shifted through, fed back, and combined witheach other by the feedback shift register structure of encoder 201. Aseach interleaved x′_(j) bit is inputted, encoder 202 similarly outputs aparity bit z′_(k). Since the systemic bits from encoder 202 are only aninterleaved version of the same systemic bits outputted by encoder 201,encoder 202 does not output x′_(j). The output from the turbo encoder inresponse to the K bits of input packet {x_(j)} thus consists of theoutputs from constituent encoder 201 and constituent encoder 202 and isequal to:x₁, z₁, z′₁, x₂, z₂, z′₂, . . . , x_(K), z_(K), z′_(K).As noted, x₁, x₂, . . . , x_(K) are the systematic bits inputted to boththe first constituent encoder 201 and to the turbo code internalinterleaver 203, K is the number of bits in the packet, and z₁, z₂, . .. , z_(K) and z′₁, z′₂, . . . , z′_(K) are the parity bits outputtedfrom the first constituent encoder 201 and the second constituentencoder 202, respectively.

After all K information bits from the input packet have been inputted toencoders 201 and 202, trellis termination is performed by taking thetail bits from the shift register feedback. Specifically, first theconstituent encoder 202 is disabled while the first three tail bits areused to terminate constituent encoder 201 by “moving” switch 206 inencoder 201 to its lower position. When in this lower position, a zerois shifted into the first shift register 204 as each bit is clockedthrough (since its input is the modulo 2 sum of two equal bits), andthen sequentially into the other shift registers. Thus, after the tailbits x_(K+1), x_(K+2), and x_(K+3) are clocked out, encoder 201 is in adesired all-zero state. Associated with these tail bits are parity bitsz_(K+1), z_(K+2) and z_(K+3), which are also clocked out. In a similarmanner, the last three tail bits are used to terminate encoder 202 whilethe encoder 201 is disabled. Thus, with switch 207 in encoder 202“moved” to its lower position, zeros are similarly clocked through eachshift register 204 and tail bits x′_(K+1), x′_(K+2), and x′_(K+3), andparity bits z′_(K+1), z′_(K+2) and z′_(K+3) are clocked out. Sinceduring trellis termination these x′_(j) tail bits are not simply aninterleaved version of the x_(j) tail bits outputted by encoder 201, theturbo encoder transmits both x_(j) and x′ for j=_(K+1) through j=_(K+3)during trellis termination. The transmitted bits for trellis terminationare thus:x_(K+1), x_(K+2), x_(K+1), z_(K+1), z_(K+2), z_(K+3), x′_(K+1),x′_(K+2), x′_(K+3), z′_(K+1), z′_(K+2), z′_(K+3).After each of these bits has been transmitted, all the shift registers204 are in the desired zero state and ready to receive input of the bitsin the next packet.

With reference to FIG. 3, a block diagram of a prior art turbo decoder301 is shown. The inputs s_(j), p_(j) and p′_(j) for j=1 to j=K are softsymbol metrics from the receiver demodulator and correspond to thetransmit bits x_(j) (the systematic bits), z_(j) (first parity bit) andz′_(j) (second parity bit) from FIG. 2, respectively. Before the decoder301 starts to decode the received bits corresponding to an input packet,all the memory units in the interleavers and deinterleavers in thedecoder are cleared to zero.

The decoding operation starts in block 302 with a systematic bits metriccalculation for the first constituent code. This block essentiallyperforms a BCJR algorithm (see, e.g., L. R. Bahl, J. Cocke, F. Jelinek,and J. Raviv, “Optimal Decoding of Linear Codes for Minimizing SymbolError Rate,” IEEE Trans. Information Theory, pp. 284-287, March 1974) toproduce a log-likelihood ratio (LLR) for each systematic bit. The signof the LLR represents the systematic bit value and its amplituderepresents the likelihood. Thus, the higher the value of the LLR, themore likely that the bit value that is indicated by the LLR's sign iscorrect. If decoding were to be stopped after this sub-block 302 at theend of this first turbo decoding cycle, the decision for each bit in thepacket delivered to the next higher layer for further processing or fora CRC check, would be determined by the sign of that bit's LLR, whichwould be mapped to a bit value by the following rule:Non-positive LLR→1, Positive LLR→0.

The transmitted second constituent code, however, enables betterperformance, i.e., improved reliability, to be achieved. By feedinginformation derived from the first constituent decoder comprisingsystematic bit metric calculation block 302 to the systematic bitsmetric calculation block 303 for the second constituent code in a nextturbo decoding cycle, advantage is taken of those systematic bit metrics(LLRs) generated from the first constituent decoder 302. Since theinterleaving performed by interleaver 203 in the turbo encoder of FIG. 2is known to the decoder 301, interleaver 304 interleaves the soft symbolmetrics s_(j) in accordance with the soft symbol metrics p′_(j) thatcorrespond to the parity bits z′_(j) transmitted by the secondconstituent encoder 202. Input to the systematic bits metric calculationblock 303 that constitutes the second decoder thus includes theseinterleaved soft symbol metrics s′_(j) and the soft symbol metricsp′_(j) corresponding to the second transmitted parity bit.

It can be noted that the received symbols metrics for the systematicbits (s_(j) and s′_(j)) are shared by both systematic bits metriccalculation blocks 302 and 303. The only information that is used by thefirst systematic bits metric calculation block 302 which cannot bedirectly used by the second systematic bits metric calculation block 303is the parity bit soft symbols metrics, p_(j), because, due to the turbointerleaving, the second systematic bits metric calculation block 303doesn't recognize the parity bits from the first code. Therefore theinformation about the systematic bits that is derived from the paritybits in the first decoder is passed to the second systematic bits metriccalculation block 303 of the second constituent decoder as a prioriinformation about the systematic bits. That information is theExtrinsic_(1,j) output of the first systematic bits metric calculationblock 302, which is obtained from:Extrinsic_(1,j) =LLR _(1,j) −s _(j)−Extrinsic_(2,j)  (2)For the initial cycle of turbo decoding the first constituent code, theExtrinsic_(2,j) term is zero for all j since the second decoder does notproduce any outputs until after the first decoder has produced its firstExtrinsic_(1,j) output.

For the second turbo decoding cycle, the second systematic bitscalculation block 303 calculates the LLRs for the interleaved systematicsoft symbol metrics s′_(j) at the output of interleaver 304 in the samemanner as the first systematic bits calculation block 302 calculated theLLRs for the systematic soft symbol metrics s_(j). The input soft symbolmetrics are the interleaved versions of the soft symbol metrics s_(j) inwhich the metrics corresponding to the tail systematic bits for thefirst constituent code are replaced with the soft symbol metricscorresponding to the tail bits of the second constituent code. TheExtrinsic_(1,j) outputs of the systematic bits metric calculation block302 are interleaved by interleaver 305 to align with the order of thes′_(j) values. The second systematic bits calculation block 303 producesthe LLRs and the Extrinsic′_(2,j), which represents information on thesystematic bits carried by p′_(j). This output is obtained from:Extrinsic′_(2,j) =LLR2_(1,j) −s′ _(j)−Extrinsic′_(1,j).  (3)

If decoding were to stop at this point, the decision for each bit in thepacket delivered to the next higher layer following the turbo decoderwould be determined by the sign of that bit's LLR, which would be mappedto a bit value, as above, by the following rule:Non-positive LLR→1, Positive LLR→0.

At this point, the turbo decoding concept comes into play by noticingthat the LLR calculation in the systematic bits metric calculation forthe first constituent code has not used the information carried byp′_(j), corresponding to the parity bits for the second constituentcode. This information is reflected in the Extrinsic′_(2,j) output ofequation (3) above. Therefore, once the Extrinsic′_(2,j) outputs areavailable, they are de-interleaved by de-interleaver 306 to align withthe order of the s_(j) and p_(j) values and fed back to the firstsystematic bits metric calculation block 302. The turbo decoding cycleperformed therein is then repeated with the updated Extrinsic′_(2,j)information to update both the LLR_(1,j) and Extrinsic′_(1,j)information calculated by that block. The updated information producedat this turbo decoding cycle can now be used to repeat the secondsystematic bits metric calculation. This process of iterative turbodecoding cycles can be made as many times as desired, with progressiveperformance improvement diminishing after ten turbo decoding iterationcycles, where one turbo decoding iteration cycle is defined as a turbodecoding cycle performed by the first constituent decoder followed by aturbo decoding cycle performed by the second constituent decoder. Thefinal decision on the systematic bits can be made based on the signs ofLLR_(1,j) or LLR_(2,j) depending on whether the process stops at theoutput of the first constituent decoder or the second constituentdecoder, respectively.

The inventors herein have realized that since the two constituent codesshare the same systematic bits, that one code can serve as the paritycheck for the other. In a first embodiment, at the end of the nth turbodecoding iteration cycle, for each systematic bit, the bit valueindicated by the sign of the LLR produced by one constituent decoder iscompared with the bit value indicated by the sign of the LLR produced bythe other constituent decoder for a corresponding systematic bit. If thesigns and thus decoded bits agree for each comparison, then the decisionis made that no packet error has occurred. Otherwise, a decision is madethat a packet error has occurred.

FIG. 4 illustrates the steps of this first embodiment. At step 401, atthe end of the nth turbo decoding iteration cycle, LLR_(1,j) is read infor each j=1 to j=K. At step 402, these LLRs are interleaved so thatthey each are aligned with a corresponding systematic bit associatedwith LLR_(2,j). At step 403, for each j, the sign of each LLR_(1,j) iscompared with the sign of LLR_(2,j) that correspond to the samesystematic bit. At step 404, a determination is made whether the sign ofeach comparison is the same. If yes, at step 405, a determination ismade that no packet error has occurred. If no, at step 406, adetermination is made that a packet error has occurred. That decisioncan then be reported to the higher layer for further processing.

FIG. 5 shows a second embodiment of the present invention in which thebits that would be decoded from the signs of the LLRs generated by thesecond constituent decoder at the end of a turbo decoding iterativecycle are compared with the bits that would be decoded from the signs ofthe LLRs generated by the same second decoder at the end of the previoustulrbo decoding iterative cycle. If the signs associated with each LLRis not the same, then the decoding is likely not converging with highprobability and the decoded sequence is in error. In this embodiment, atstep 501, at the (n−1)th turbo iteration cycle, LLR_(2,j) is read in forall j=1 to j=K. At step 502, at the nth turbo decoding iteration cycle,LLR_(2,j) is read in for all j=1 to j=K. Since the LLRs for the same jcorrespond to the same systematic bit, no de-interleaving is necessary.At step 503, the sign of LLR_(2,j) at the (n−1)th iteration is comparedwith the sign of LLR_(2,j) at the nth iteration cycle for each j. Atstep 504, a determination is made whether the signs are the same foreach comparison. If yes, then, at step 505, a determination is made thatthere has been no packet error. If no, then, at step 506, adetermination is made there has been a packet error.

Similar results could be achieved by comparing the signs of the LLRsproduced by either the first or second decoder at the end of a turbodecoding cycle with the signs of the LLRs that correspond to the samesystematic bits and which are produced by the first or second decoder atthe end of any preceding turbo decoding cycle, whether within the sameturbo decoding iterative cycle or different turbo decoding iterativecycles.

While the particular invention has been described with reference to theillustrative embodiments, this description should not be construed in alimiting sense. It is understood that although the present invention hasbeen described, various modifications of the illustrative embodiments,as well as additional embodiments of the invention, will be apparent toone of ordinary skill in the art upon reference to this descriptionwithout departing from the spirit of the invention, as recited in theclaims appended hereto. Although being noted as applicable to 3GPP2CDMA2000-1× and 3GPP UMTS W-CDMA standards, the present invention couldbe implemented in any CDMA or non-CDMA, wireless or wired electrical oroptical communication system that uses turbo encoding and decoding.Further, the invention may be implemented in different locations, suchas a base station (NodeB in UMTS terminology) or a mobile terminal (UEin UMTS terminology), or anywhere else where turbo decoding might beperformed. The processing circuitry required to implement and use thedescribed invention may be implemented in application specificintegrated circuits, software-driven processing circuitry, firmware,programmable logic devices, hardware, discrete components orarrangements of the above components as would be understood by one ofordinary skill in the art with the benefit of this disclosure. Thoseskilled in the art will readily recognize that these and various othermodifications, arrangements and methods can be made to the presentinvention without strictly following the exemplary applicationsillustrated and described herein and without departing from the spiritand scope of the present invention. It is therefore contemplated thatthe appended claims will cover any such modifications or embodiments asfall within the true scope of the invention.

1. A method at a turbo decoder for detecting an error in a block ofdecoded bits comprising: comparing on a bit-by-bit basis within theblock decoded systematic bit values determined at the end of a firstturbo decoding cycle with corresponding decoded systematic bit valuesdetermined at the end of a previous turbo decoding cycle; anddetermining from the results of the bit-by-bit comparisons whether ornot there is an error in the decoded systematic bit values in the blockof decoded bits determined at the end of the first turbo decoding cycle.2. The method of claim 1 wherein the previous turbo decoding cycle isany turbo decoding cycle previous to the first turbo decoding cycle. 3.The method of claim 1 wherein the step of determining determines thatthere is an error if one or more comparisons of corresponding bit valuesdoes not match.
 4. The method of claim 1 wherein the step of determiningdetermines that there is no error if the comparisons of correspondingbit values all match.
 5. The method of claim 1 wherein the step ofcomparing decoded systematic bit values comprises comparing forcorresponding bits signs of log likelihood ratios determined at the endof a first turbo decoding cycle with signs of log likelihood ratiosdetermined at the end of any previous turbo decoding cycle.
 6. Themethod of claim 5 wherein the end of the first turbo decoding cycle isthe end of a turbo decoding cycle within a turbo decoding iterationcycle in which a second turbo constituent code is decoded and whereinthe end of the previous turbo decoding cycle is the end within the sameturbo decoding iteration cycle of the turbo decoding cycle in which afirst turbo constituent code is decoded.
 7. The method of claim 5wherein the end of the first turbo decoding cycle is the end of a firstturbo decoding iteration cycle and the end of the previous turbodecoding cycle is the end of a decoding iteration cycle that precedesthe first turbo decoding iteration cycle, a decoding iteration cyclecomprising a turbo decoding cycle in which a first turbo constituentcode is decoded followed by a turbo decoding cycle in which a secondturbo constituent code is decoded.
 8. The method of claim 5 wherein thestep of determining determines that there is an error if one or morecomparisons of the signs of log likelihood ratios associated withcorresponding bits does not match.
 9. The method of claim 5 wherein thestep of determining determines that there is no error if the comparisonsof log likelihood ratios associated with corresponding bits values allmatch.
 10. Apparatus for detecting an error in a block of bits decodedby a turbo decoder that comprises a first constituent turbo decoder anda second constituent turbo decoder, the apparatus comprising: means forcomparing on a bit-by-bit basis within the block decoded systematic bitvalues determined at the end of a first turbo decoding cycle withcorresponding decoded systematic bit values determined at the end of aprevious turbo decoding cycle; and means for determining from theresults of the bit-by-bit comparisons made by the comparing meanswhether or not there is an error in the decoded systematic bit values inthe block of decoded bits determined at the end of the first turbodecoding cycle.
 11. The apparatus of claim 10 wherein the previous turbodecoding cycle is any turbo decoding cycle previous to the first turbodecoding cycle.
 12. The apparatus of claim 10 wherein the determiningmeans determines that there is an error if one or more comparisons madeby the comparing means of corresponding bit values does not match. 13.The apparatus of claim 10 wherein the determining means determines thatthere is no error if the comparisons made by the comparing means ofcorresponding bit values all match.
 14. The apparatus of claim 10wherein the comparing means compares for corresponding bits signs of loglikelihood ratios determined at the end of a first turbo decoding cyclewith signs of log likelihood ratios determined at the end of anyprevious turbo decoding cycle.
 15. The apparatus of claim 14 wherein theend of the first turbo decoding cycle is the end of a turbo decodingcycle within a turbo decoding iteration cycle in which the second turboconstituent decoder decodes a second turbo constituent code, and whereinthe end of the previous turbo decoding cycle is the end within the sameturbo decoding iteration cycle of the turbo decoding cycle in which thefirst constituent decoder decodes a first turbo constituent code. 16.The apparatus of claim 14 wherein the end of the first turbo decodingcycle is the end of a turbo decoding iteration cycle in which the secondturbo constituent decoder decodes the second turbo constituent code, andthe end of the previous turbo decoding cycle is the end of a decodingiteration cycle that precedes the first turbo decoding iteration cycleand in which the second turbo constituent decoder decodes the secondturbo constituent code, a decoding iteration cycle comprising a turbodecoding cycle in which the first turbo constituent decoder decodes afirst turbo constituent code followed by a turbo decoding cycle in whichthe second turbo constituent decoder decodes the second turboconstituent code.
 17. The apparatus of claim 14 wherein the determiningmeans determines that there is an error if one or more comparisons madeby the comparing means of corresponding bit values does not match. 18.The method of claim 14 wherein the determining means determines thatthere is no error if the comparisons made by the comparing means ofcorresponding bit values all match.